top of page

Publications

Journal Paper

  1.  W. C.-Y. Ma, C.-J. Su, K.-H. Kao, et al., “Ferroelectric tunnel thin-film transistor for synaptic applications,” ECS J. Solid State Sci. Technol., 12, 055006, 2023.

  2. W. C.-Y. Ma, C.-J. Su, K.-H. Kao, et al., “Impacts of pulse conditions on endurance behavior of ferroelectric thin-film transistor non-volatile memory”, Semicond. Sci. Technol., 38, 3, 035020, 2023.

  3. W.-J. Lee, W.-T. Hsieh, B.-H. Fang, K.-H. Kao* and N.-Y Chen, “Device Simulations with A U-Net Model Predicting Physical Quantities in Two-Dimensional Landscapes”, Sci. Rep., 13, 731, 2023.

  4. S.-W. Chang, T.-H. Lu, C.-Y. Yang, C.-J. Yeh, M.-K. Huang, C.-F. Meng, P.-J. Chen, T.-H. Chang, Y.-S. Chang, J.-W. Jhu, T.-C. Hong, C.-C. Ke, X.-R. Yu, W.-H. Lu, M. Baig, T.-C. Cho, P.-J. Sung, C.-J. Su, F.-K. Hsueh, B.-Y. Chen, H.-H. Hu, C.-T. Wu, K.-L. Lin, W. C.-Y. Ma, D. Lu, K.-H. Kao, et al., “First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications”, IEEE Trans. Electron Devices, 69, 2101, 2022.

  5. K. Kumar, C.-H. Lo, C.-C. Chang, T.-L. Wu, K.-H. Kao* and Y. -H. Wang, "Impacts of material parameters on breakdown voltage and location for power MOSFETs," J. Computational Electronics, 21, 1163, 2022.

  6. K.-H. Kao*, et al., “Linking Room- and Low-Temperature Electrical Performance of MOS Gate Stacks for Cryogenic Applications”, IEEE Electron Device Lett., 43, 674, 2022.

  7.  W. C.-Y. Ma, C.-J. Su, K.-H. Kao, et al., “First demonstration of ferroelectric tunnel thin-film transistor non-volatile memory with polycrystalline-silicon channel and HfZrOx gate dielectric”, IEEE Trans. Electron Devices, 69, 11, 6072, 2022.

  8. W. C.-Y. Ma, C.-J. Su, K.-H. Kao, et al., “Demonstration of synaptic characteristics of polycrystalline-silicon ferroelectric thin-film transistor for application of neuromorphic computing”, Semicond. Sci. Technol., 37, 4, 045003, 2022.

  9. S.-W. Tang, Z.-H. Huang, Y.-C. Chen, C.-H. Wu, P.-H. Lin, Z.-C. Chen, M.-H. Lu, K.-H. Kao, and T.-L. Wu, "Investigation of the Passivation-induced VTH Shift in p-GaN HEMTs with Au-free Gate-first Process ," Microelectronics Reliability, 122, 114150, 2021.

  10. Y. Fang, W.-J. Lee, A.-C. Yang, G.-P. Chen, N.-Y. Chen and K.-H. Kao*, “Inherent Dipole Layer Formation Driven by Surface Energy at Nonplanar Dielectric Interfaces”, IEEE Trans. Electron Devices, 68, 294, 2021.

  11. T.-H. Yang, C.-J. Su, Y.-S. Wang, K.-H. Kao, et al., "Impact of the Polarization on Time-Dependent Dielectric Breakdown in Ferroelectric Hf0.5Zr0.5O2 on Ge Substrates," J. J. Appl. Phys., 59, SGGB08, 2020.

  12. K.-H. Kao*, et al., “Subthreshold Swing Saturation of Nanoscale MOSFETs Due to Source-to-Drain Tunneling at Cryogenic Temperatures”, IEEE Electron Device Lett., 41, 1296, 2020.

  13. P.-J. Sung, S.-W. Chang, K.-H. Kao, et al., “Fabrication of Vertically Stacked Nanosheet Junctionless Filed-Effect Transistors and Applications for the CMOS and CFET Inverters”, IEEE Trans. Electron Devices, 67, 3504, 2020.

  14. T. H. Yang, C.-J. Su, Y.-S. Wang, K.-H. Kao, et al., “Impact of the Polarization on Time-Dependent Dielectric Breakdown in Ferroelectric Hf0.5Zr0.5O2 on Ge Substrates”, Jpn, J. App. Phys., 59, SGGB08, 2020.

  15. S.-H. Chen, S.-W. Lian, T.-R. Wu, T.-R. Chang, J.-M. Liou, D. D. Lu, K.-H. Kao*, et al., “Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs”, IEEE Trans. Electron Devices, 66, 2509, 2019.

  16. K. Kumar, Y.-F. Hsieh, J.-H. Liao, K.-H. Kao*, et al., “Significance of Multivalley and Nonparabolic Band Structure for GeSn TFET Simulation”, IEEE Trans. Electron Devices, 65, 4709, 2018.

  17. V. Kumar M P, J-Y Lin, K.-H. Kao, et al., “Junctionless FETs with a Fin Body for Multi-VTH and Dynamic Threshold Operation”, IEEE Trans. Electron Devices, 65, 3535, 2018.

  18. Y.-F. Hsieh, S.-H. Chen, N.-Y. Chen, W.-J. Lee, J.-H. Tsai, C.-N. Chen, M.-H. Chiang, D. D. Lu and K.-H. Kao*, “A FET with a Source Tunneling Barrier Showing Suppressed Short Channel Effects for Low Power Applications”, IEEE Trans. Electron Devices, 65, 855, 2018.

  19. (Invited) L.-Y. Chen and K.-H. Kao*, “金屬-絕緣層-半導體接面之無摻雜場效應電晶體”, National Nano Device Laboratories (NDL) Communications, 25, 1, 2018.

  20. S.-S. Chuang, T.-C. Cho, P.-J. Sung, K.-H. Kao, et al., “Ultra-Shallow Junction Formation by Molecular Doping Process in Single Crystalline Si and Ge for Future CMOS Devices”, ECS J. Solid State Science and Tech., 6 (5), 350, 2017.

  21. V. Kumar M P, C.-Y. Hu, A. M. Walke, K.-H. Kao*, et al., “Improving the Electrical Performance of a Shell Doping Profile Quantum Well Transistor by Heterojunction Optimization”, IEEE Trans. Electron Devices, 64, 3563, 2017.

  22. L. Y. Chen, Y.-F. Hsieh and K.-H. Kao*, “Undoped and Doped Junctionless FETs: Source/Drain Contacts and Immunity to Random Dopant Fluctuation”, IEEE Electron Device Lett., 38, 708, 2017.

  23. K.-H. Kao*, et al., “A Dopingless FET with Metal-Insulator-Semiconductor Contacts”, IEEE Electron Device Lett., 38, 5, 2017.

  24. V. Kumar M P, C.-Y. Hu, K.-H. Kao*, et al., “Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs”, IEEE Trans. Electron Devices, 62, 3541, 2015.

  25. K.-H. Kao*, et al., “Compressively strained SiGe band-to-band tunneling model calibration based on p-i-n diodes and prospect of strained SiGe tunneling field-effect transistors”, J. Appl. Phys., 116, 214506, 2014.

  26. K.-H. Kao*, et al. “Tensile strained Ge tunnel field-effect transistors: k·p material modeling and numerical device simulation”, J. Appl. Phys., 115, 044505, 2014.

  27. A. M. Walke, A. Vandooren, R. Rooyackers, D. Leonelli, D. Hikavy, R. Loo, A. S. Verhulst, K.-H. Kao, et al., “Fabrication and analysis of a Si/Si0.55Ge0.45 hetero-junction line tunnel FET”, IEEE Trans. Electron Devices, 61, 707, 2014.

  28. A. M. Walke, W. G. Vandenberghe, K.-H. Kao, et al., “A simulation study on process sensitivity of a line tunnel field-effect transistor”, IEEE Trans. Electron Devices, vol. 60, 1019, 2013.

  29. D. Verreck, A. S. Verhulst, K.-H. Kao, et al., “Quantum mechanical performance predictions of p-n-i-n versus pocketed line tunnel field-effect transistors”, IEEE Trans. Electron Devices, 60, 2128, 2013.

  30. K.-H. Kao*, et al., “Counter-doped pocket thickness optimization of gate-on-source-only tunnel FETs”, IEEE Trans. Electron Devices, 60, 6, 2013.

  31. K.-H. Kao*, et al., “Optimization of gate-on-source-only tunnel FETs with counter-doped pockets”, IEEE Trans. Electron Devices, 59, 2070, 2012.

  32. K.-H. Kao*, et al., “Direct and indirect band-to-band tunneling in germanium-based TFETs,” IEEE Trans. Electron Devices, 59, 292, 2012.

  33. K.-H. Kao*, et al., “Modeling the impact of junction angles in tunnel field-effect transistors”, Solid State Electron., 69, 31, 2012.

  34. W. G. Vandenberghe, A. S. Verhulst, K.-H. Kao, et al., “A model determining optimal doping concentration and material’s band gap of tunnel field-effect transistors,” Appl. Phys. Lett., 100, 193509, 2012.

  35. K.-H. Kao, et al., “X-ray photoelectron spectroscopy energy band alignment of spin-on CoTiO3 high-k dielectric prepared by sol-gel spin coating method,” Appl. Phys. Lett., 93, 092907, 2008.

Conference Paper

  1. W.-C. Lin, H.-P. Huang, K.-H. Kao*, et al., “MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization”, IEEE ESSDERC, 2023.

  2. H.-L. Chiang, R. A. Hadi, J.-F. Wang, H.-C. Han, J.-J. Wu, H.-H. Hsieh, J.-J. Horng, W.-S. Chou, B.-S. Lien, C.-H. Chang, Y.-C. Chen, Y.-H. Wang, T.-C. Chen, J.-C. Liu, Y.-C. Liu, M.-H. Chiang, K.-H. Kao, et al., “How Fault-Tolerant Quantum Computing Benefits from Cryo-CMOS Technology”, VLSI Tech. Dig., accepted, 2023.

  3. C.-Y. Yang, P.-J. Sung, M.-H. Chuang, C.-W. Chang, Y.-J. Shih, T.-Y. Huang, D. Lu, T.-C. Hong, X.-R. Yu, W.-H. Lu, S.-W. Chang, J.-J. Tsai, M.-K. Huang, T.-C. Cho, Y.-J. Lee, K.-L Luo, C.-T. Wu, C.-J. Su, K.-H. Kao, et al., “First Demonstration of Heterogeneous L-shaped Field Effect Transistor (LFET) for Angstrom Technology Nodes”, IEEE IEDM Tech. Dig., 20.2.1, 2022.

  4. X.-R. Yu, M.-H. Chuang, S.-W. Chang, W.-H. Chang, T.-C. Hong, C.-H. Chiang, W.-H. Lu, C.-Y. Yang, W.-J. Chen, J.-H. Lin, P.-H. Wu, T.-C. Sun, S. Kola, Y.-S. Yang, Yun Da, P.-J. Sung, C.-T. Wu, T.-C. Cho, G.-L. Luo, K.-H. Kao, et al., “Integration Design and Process of 3-D Heterogeneous 6T SRAM with Double Layer Transferred Ge/2Si CFET and IGZO Pass Gates for 42% Reduced Cell Size”, IEEE IEDM Tech. Dig., 20.5.1, 2022.

  5. X.-R. Yu, W.-H Chang, T.-C. Hong, P.-J. Sung, A. Agarwal, G.-L. Luo, C.-T. Wu, K.-H. Kao, et al., “First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering”, VLSI Tech. Dig., 399, 2022.

  6. S.-W. Chang, T.-H. Lu, C.-Y. Yang, C.-J. Yeh, M.-K. Huang, C.-F. Meng, P.-J. Chen, T.-H. Chang, Y.-S. Chang, J.-W. Jhu, T.-Z. Hong, C.-C. Ke, X.-R. Yu, W.-H. Lu, M. A. Baig, T.-C. Cho, P.-J. Sung, C.-J. Su, F.-K. Hsueh, B.-Y. Chen, H.-H. Hu, C.-T. Wu, K.-L. Lin, W. C.-Y. Ma, D.-D. Lu, K.-H. Kao, et al., “First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications”, IEEE IEDM Tech. Dig., 34.4.1, 2021.

  7. C. J. Su, M. K. Huang, K. S. Lee, V. P. H. Hu, Y. F. Huang, B. C. Zheng, C. H. Yao, N. C. Lin, K. H. Kao, et al., “3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers”, IEEE IEDM Tech. Dig., 12.2.1, 2020.

  8. T.-Z. Hong, W.-H. Chang, A. Agarwal, Y.-T. Huang, C.-Y. Yang, T.-Y. Chu, H.-Y. Chao, Y. Chuang, S.-T. Chung, J.-H. Lin, S.-M. Luo, C.-J. Tsai, M.-J. Li, X.-R. Yu, N.-C. Lin, T.-C. Cho, P.-J. Sung, C.-J. Su, G.-L. Luo, F.-K. Hsueh, K.-L. Lin, H. Ishii, T. Irisawa, T. Maeda, C.-T. Wu, W. C.-Y. Ma, D.-D. Lu, K.-H. Kao, et al., “First Demonstration of Heterogeneous Complementary FETs Utilizing Low-Temperature (200 oC) Hetero-Layers Bonding Technique (LT-HBT)”, IEEE IEDM Tech. Dig., 15.5.1, 2020.

  9. C.-J. Su, P.-J. Sung, K.-H. Kao, et al., “Process and Structure Considerations for the Post FinFET Era”, IEEE SNW, 3.1, 13, 2020.

  10. S.-W. Chang, et al., “First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications”, IEEE IEDM Tech. Dig., 11.7, 2019.

  11.  Y.-T. Tang, C.-L. Fan, Y.-C. Kao, N. Modolo, C.-J. Su, T.-L. Wu, K.-H. Kao, et al., “A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs”, VLSI Tech. Dig., T17-2, 2019.

  12. P.-J. Sung, C.-J. Su, D. D. Lu, S.-X. Luo, K.-H. Kao, et al., “Fabrication of Ω-gated Negative Capacitance FinFETs and SRAM”, VLSI-TSA, 2019.

  13. P.-J. Sung, C.-Y. Chang, L.-Y. Chen, K.-H. Kao, et al., “Voltage Transfer Characteristics Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs Application”, IEEE IEDM Tech. Dig., 21.4, 2018.

  14. Y.-T. Tang, C.-J. Su, Y.-S. Wang, K.-H. Kao, et al., “A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5nm Node”, VLSI Tech. Dig., 45, 2018.

  15. Yu Fang, W.-J. Lee, L.-Y. Chen, N.-Y. Chen, J.-H. Tsai and K.-H. Kao, "Molecular Dynamics Simulations of Dipole Layer Formation in Gate-All-Around Structure", IEEE SNW, 2-31, 2018.

  16. L.-Y. Chen, Ankit Agarwal, Yu Fang, S.-H. Chen and K.-H. Kao, "Dopingless Si Nanowire Transistor", International Congress of Engineering and Information, Accepted, 2018.

  17. C.-J. Su, T.-C. Hong, Y.-C. Tsou, F.-J. Hou, P.-J. Sung, M.-S. Yeh, C.-C. Wan, K.-H. Kao, et al., “Ge Nanowire FETs with HfZrOx Ferroelectric Gate Stack Exhibiting SS of Sub-60 mV/dec and Biasing Effects on Ferroelectric Reliability” IEEE IEDM Tech. Dig., 15.4, 2017.

  18. C.-J. Su, Y.-T. Tang, Y.-C. Tsou, P.-J. Sung, F.-J. Hou, C.-J. Wang, S.-T. Chung, C.-Y. Hsieh, Y.-S. Yeh, F.-K. Hsueh, K.-H. Kao, et al., “Nano-scaled Ge FinFETs with Low Temperature Ferroelectric HfZrOx on Specific Interfacial Layers Exhibiting 65% S.S. Reduction and Improved ION” VLSI Tech. Dig., T12-1, 2017.

  19.  L.-Y. Chen, Y.-F. Hsieh and K.-H. Kao, “Undoped SiGe FETs with Metal-Insulator-Semiconductor Contacts”, IEEE SNW, 5-33, 2017.

  20. Y.-J. Lee, T.-C. Hong, F.-K. Hsueh, P.-J. Sung, C.-Y. Chen, S.-S. Chang, T.-C. Cho, S. Noda, Y.-C. Tsou, K.-H. Kao, et al., “High Performance Complementary Ge Peaking FinFETs by Room Temperature Neutral Beam Oxidation for Sub-7 nm Technology Node Applications”, IEEE IEDM Tech. Dig., 33.5, 2016.

  21. Y.-J. Lee, F.-J. Hou, S.-S. Chang, F.-K. Hsueh, K.-H. Kao, et al., “Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technology”, IEEE IEDM Tech. Dig., 15.1, 2015.

  22. Y.-J. Lee, T.-C. Cho, P.-J Sung, K.-H. Kao, et al., “High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications”, IEEE IEDM Tech. Dig., 6.2, 2015.

  23. Y.-J. Lee, T.-C. Cho, K.-H. Kao, et al., “A Novel Junctionless FinFET Structure with sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing”, IEEE IEDM Tech. Dig., 32.7, 2014.

  24. A. S. Verhulst, D. Verreck, Q. Smets, K.-H. Kao, et al., “Perspective of Tunnel-FET for Future Low-Power Technology Nodes”, IEEE IEDM Tech. Dig., 30.2, 2014 (invited).

  25. Q. Smets, A. S. Verhulst, R. Rooyackers, C. Merckling, D. Lin, E. Simoen, A. Alian, M. Cantoro, A. Pourghaderi, K.-H. Kao, et al., “InGaAs diodes for band-to-band tunneling calibration and n- and p- lineTFET performance prediction”, SSDM, 752-753, 2013.

  26. A. S. Verhulst, W. G. Vandenberghe, K.-H. Kao, et al., “Tunnel field-effect transistors for low-power nano-electronics”, 2013 9th international nanotechnology conference on communication and cooperation, Berlin, Germany.

  27. A. Vandooren, A. S. Verhulst, R. Rooyackers, A. M. Walke, K.-H. Kao, et al., “Trends and challenges in tunnel field effect transistors”, “2013 7th international workshop “functional nanomaterials and devices for electronics, sensors, energy harvesting”, Ukraine.

  28.  K.-H. Kao, et al., “SiGe band-to-band tunneling calibration based on p-i-n diodes: fabrication, measurement and simulation”, ECS Transactions, 50, 965-970, 2012.

  29.  K.-H. Kao, et al., “The impact of junction angle on tunnel FETs”, Proceedings of Ultimate Integration on Silicon (ULIS), p. 80-83, 2011.

  30. A. S. Verhulst, W. G. Vandenberghe, D. Leonelli, R. Rooyackers, A. Vandooren, J. Zhuge, K.-H. Kao, et al., “Si-based tunnel field-effect transistors for low-power nano-electronics”, DRC, 193, 2011.

  31. W.-C. Wu, C.-S. Lai, S.-C. Lee, M.-W. Ma, T.-S. Chao, J.-C. Wang, C.-W. Hsu, P.-C. Chou, J.-H. Chen, K.-H. Kao, et al., “Fluorinated HfO2 Gate Dielectrics Engineering for CMOS by pre- and post-CF4 Plasma Passivation,” IEDM Tech. Dig., 405, 2008.

  32. K.-H. Kao, et al., “Characterization of CoTiO3 Thin Films Formed by Sol-Gel Spin Coating with High Temperature Annealing”, SNDT 2007 Symposium on Nano Device Technology, Taiwan.

bottom of page